1. Field of the Invention
The present invention relates generally to integrated circuit comparators, and, more particularly, to integrated circuit comparators for use in low voltage applications.
2. Description of the Related Art
A conventional CMOS voltage comparator 10 is illustrated in FIG. 1. The CMOS voltage comparator 10 includes a differential amplifier 11 and an inverter 12. A reference voltage VR is applied to one input of the differential amplifier 11, i.e., a gate terminal of a transistor 21, and an input voltage V1 to be compared to the reference voltage is applied to another input to the differential amplifier 11, i.e., a gate terminal of a transistor 22. In operation, when the input voltage V1 becomes higher than the reference voltage VR, an output signal on a line 25 switches from a low voltage, for example, a logic level “zero,” to a high voltage, for example, a logic level “one.” When the input voltage VI becomes lower than the reference voltage VR, the transistor 22 turns off, the input signal to the inverter 12 becomes high, and the output signal VOUT changes from a high state to a low state. In this manner, the input voltage VI is compared to the reference voltage VR. Ideally, the transition between logic levels at the output line 25 will occur when V1 is equal to VR, there being no offset voltage. Also ideally, the transition between logic levels will occur with no time delay, the speed of the comparator 10 being very fast. These ideals are rarely, if ever, attained.
Comparators are widely used in integrated circuits, for example, in analog-to-digital converters and as voltage signal receivers on interconnections and clock distribution lines. Two primary concerns in the application of comparators are the mismatch of transistor characteristics, resulting in voltage offsets, and the speed of operation, or time delay in operation. Because one of the basic components of a comparator is a differential amplifier, which typically involves three transistors coupled in series, operation of the comparator becomes slower and less reliable as power supply voltages are reduced. Lower power supply voltages result in lower magnitudes of the excess of gate voltage above the threshold voltage of the MOS transistors. The switching current, or saturation current, depends upon the square of this excess gate voltage:Ids=(uCo)(W/L)(VGS−VT)2/2The time, t, required to discharge a capacitor with charge Q can be estimated as:t=Q/Ids If the excess of gate-to-source voltage above threshold (VGS−VT) is small, the delay time will be long, and the circuits will operate at low switching speeds.
The inverter 12 of FIG. 1 is a conventional single-ended input, single-ended output, CMOS amplifier. To illustrate the operation of the inverter amplifier 12, assume a power supply potential 26 is 1.6 volts, i.e., VDD equals 1.6 volts DC. Assume further that the quiescent input and output voltages are at VDD/2, or 0.8 volts DC. Both the PMOS transistor 28 and the NMOS transistor 30 are assumed, for purposes of illustration, to have matching characteristics and matching threshold voltages of 0.5 volts. That is, VTN equals 0.5 volts, and VTP equals −0.5 volts. In practice, different sizes or W/L ratios can be used to compensate for the fact that the transistors do not have matching characteristics. Assuming the stated values, the turn-on time for the inverter amplifier 12 is approximately three nanoseconds, whereas, the turn-off time for the inverter amplifier 12 is on the order of tens of nanoseconds.
Low switching speeds and circuit functional failure at low power supply voltages are even more acute in differential amplifiers that form part of a comparator circuit, such as the comparator circuit 10 of FIG. 1. In the differential amplifier 11 of the comparator circuit 10 of FIG. 1, three devices, transistors 21, 23, 24, are coupled in series between the power supply potential 26 and the power supply ground 29. Also, three other transistors 22, 24, 27 are coupled in series between the power supply potential 26 and the power supply ground 29. Each of the transistors 21, 22, 23, 24, 27 needs a reasonable magnitude of excess gate voltage above threshold to operate properly. With the power supply potential 26 equal to 1.5 volts DC, the turn-on time for the comparator 10 is just over one nanosecond, while the turn-off time is on the order of 3-4 nanoseconds. When the power supply potential 26 is dropped to 1.2 volts DC, the turn-on time lengthens to approximately 4 nanoseconds, while the turn-off time lengthens to approximately 6 nanoseconds. When the power supply potential 26 is dropped even further, to 0.9 volts DC, the turn-on time for the comparator 10 is again approximately 4 nanoseconds, but the turnoff time approaches 10 nanoseconds, becoming so long that the comparator 10 begins to function incorrectly.
The present invention is directed to eliminating, or at least reducing the effects of, some or all of the aforementioned problems.